Upcoming Webinar

FPGA for DSP applications: Fixed Point Made Easy

May 16, 2017
Session 1:
9:00 a.m. U.S. EDT/ 2:00 p.m. BST/ 3:00 p.m. CEST
Session 2:
2:00 p.m. U.S. EDT/ 7:00 p.m. GMT/ 8:00 p.m. CEST


This session explains how to take Signal Processing and Communications designs from floating point to efficient fixed point implementation on FPGAs. The presentation will cover the theory of fixed point mathematics, hardware optimizations, and how to achieve this using MathWorks tools.

Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.

About the Presenter

As a senior applications engineer, Jeff Miller focuses on supporting customers for adopting HDL code generation and LTE technology. Customer projects have included HDL designs for high performance FFT, FIR, Matrix Mathematics, Encryption, Custom Floating Point, and LTE receivers. Prior to joining MathWorks, Jeff worked at Applied Signal Technology doing Signal Intelligence, and at Morphics Technology doing commercial wireless communications. Jeff has a Master’s of Electrical Engineering from Georgia Tech and a Master’s of Education from the University of Arizona.

Product Focus

  • Fixed-Point Designer
  • HDL Coder
  • MATLAB Coder