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Connecting Simulink with your SystemVerilog Workflow for Functional Verification

Date: August 19, 2014
Session 1: 9:00 a.m. U.S. EDT / 2:00 p.m. GMT+1 / 3:00 p.m. CEST
Session 2: 2:00 p.m. U.S. EDT / 7:00 p.m. GMT+1 / 8:00 p.m. CEST


Learn how you can increase the productivity of your FPGA and ASIC verification process by exporting MATLAB and Simulink models into your SystemVerilog environment at this webinar.

Using HDL Verifier, with Embedded Coder, you can export a Simulink subsystem as a SystemVerilog component, with a Direct Programming Interface (DPI) for behavioral simulation. You can model and export algorithms, components, environment models and data sources using this technology.

With this workflow you can:

  1. Generate C code from your Simulink model
  2. Automatically wrap the C code using the DPI-C interface
  3. Import, build and simulate an equivalent behavioral SystemVerilog model in your IC design tool
Please allow approximately 60 minutes to attend the presentation and Q&A session.

About the Presenters

Sudeepa Prakash is product marketing manager for HDL code generation and verification products at MathWorks. Prior to joining MathWorks, she was an embedded software engineer at Johnson Controls Inc. Sudeepa has also worked with scientists at LRDE in India on digital modules for radar systems using HDL code generation. She has a master’s degree in computer science from the University of Wisconsin- Milwaukee and a bachelor’s in electronics and communications from Visvesvaraya Technological University.

Dr. Giorgia Zucchelli is product marketing manager for RF and mixed-signal at MathWorks. Before moving to this role in 2012, she spent three years as an application engineer focusing on signal processing and communications systems and specializing in analog simulation. Before joining MathWorks in 2009, Giorgia worked at NXP Semiconductors on mixed-signal verification methodologies and at Philips Research developing system-level models for innovative telecommunication systems. Giorgia has a master’s degree in electronic engineering and a doctorate in electronics for telecommunications from the University of Bologna. Her thesis dealt with modeling high-frequency RF devices.

Product Focus

  • HDL VerifierTM

Connecting Simulink with your SystemVerilog Workflow for Functional Verification

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